Those skilled in the art are familiar with the structure and operation of metal oxide semiconductor field effect transistor (MOSFET) devices. Such devices include source, drain and channel regions formed in a semiconductor substrate as well as a gate formed over the channel region. The gate includes a gate oxide layer and a conductive gate stack insulated from the channel region by the gate oxide layer. The conductive gate stack may, for example, include a layer of a metal nitride (for example, titanium nitride TiN) physically adjacent the gate oxide and one or more other metal layers and/or semiconductor layers over the metal nitride layer.
It is often important for two or more MOSFET devices of an integrated circuit to be designed identically, in an identical environment, and operated identically. However, two identically designed MOSFET devices placed side by side in an integrated circuit may operate differently such as by having slightly different threshold voltages (Vt). Indeed, as the sizes (width and/or length) of the designed transistors decreases, experimentation has shown that the local variability of threshold voltage between identical transistors increases for dimensions above 1 μm (for length) or 1 μm2 (for surface area=length×width). This can be a problem when correct circuit operation relies on the use of matched transistors.
One source of threshold voltage variability is traced to the work function (WF) of the metal gate. More specifically, the metal gate WF depends on orientation of the grains for the WF material. Taking TiN as an example, a crystallographic orientation of (200) has a corresponding WF of 4.6 eV while a crystallographic orientation of (111) has a corresponding WF of 4.4 eV. There is a corresponding increase in threshold voltage variability with grain size for the WF material.
A solution to the concern with threshold voltage variability is to reduce WF material variation among otherwise identically designed transistor devices. For example, a long duration and high temperature metal gate deposition process can achieve large grain size of a single orientation. Conversely, a short duration and low temperature metal gate deposition process can produce no grain growth, with a large number of small grains yielding a negligible WF variation. In an ideal case, an amorphous metal gate is preferred.
The foregoing is illustrated in FIGS. 1A-1C, 2A-2C and 3A-3D. FIGS. 1A-1C illustrate a metal nitride layer 10 over a high-k dielectric layer 12 such as would be common for use in a MOSFET device supported on a substrate 14 that would include the drain, source and channel regions. The characteristics of the high-k dielectric layer 12 are the same in each of FIGS. 1A-1C. The morphology of the metal nitride layer 10, however, differs across FIGS. 1A-1C. FIG. 1A illustrates a morphology characterized by relatively larger-size grains (for example, >10 nm) referred to as category I. FIG. 1B illustrates a morphology characterized by nano-sized grains (for example, 1-10 nm) referred to as category II. FIG. 1C illustrates a morphology characterized by amorphous material, or nanocrystallites with a size <1 nm, referred to as category III. With respect to the grains in FIGS. 1A and 1B, the grains may exhibit different crystallographic orientations. For example, the grains may have a (110) orientation 16, a (100) orientation 18 or a (111) orientation 20 (it being understood that these orientations are merely examples not to be considered limiting). With reference to FIGS. 2A-2C, the work function (WF) ϕ is shown for three different types of materials (Type A in FIG. 2A, Type B in FIG. 2B and Type C in FIG. 2C) over at least three different grain orientations. In type A, the film is strongly textured in a single preferential grain orientation. In type B, the film has a few grain orientations of equivalent importance. In type C, the film has no preferential grain orientation. It will be noted that a significant variation in WF can arise with respect different material types in different crystallographic orientations. FIGS. 3A-3C show variation in work function ϕ along a distance for different combinations of the morphology of FIGS. 1A-1C and material type of FIGS. 2A-2C. For example, FIG. 3A shows the variation in ϕ as a function of distance for a category I morphology and a Type A material. FIG. 3B shows the variation in ϕ as a function of distance for a category I morphology and a Type B material. FIG. 3C shows the variation in ϕ as a function of distance for a category III morphology and a Type C material. As noted above, FIG. 3C shows than an amorphous metal gate (or with nano grains of size <1 nm) would be preferred with respect to work function variation because orientation is averaged over many different tiny grains. However, subsequent thermal budgets needed to complete the MOSFET manufacturing process (e.g. Source/Drain anneal, raised Source/Drain epitaxy) will cause the recrystallization of the amorphous metal gate. The inventors have noticed that when amorphous titanium nitride (TiN) is deposited to form the gate work function material, the amorphous TiN tends to recrystallize in columnar structure, corresponding to a morphology of Type I in relation to FIG. 3A. This nullified the potential benefit of amorphous TiN for so-called Gate-First MOSFET integration or for MOSFET devices on Fully Depleted Silicon On Insulator (FD-SOI).
With respect to TiN as a work function material, those skilled in the art understand that conventional semiconductor processes for the deposit of a TiN layer, such as physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD), produce a micromorphology that is characterized as being columnar. A columnar structure exhibits well-defined crystallographic planes producing an angular profile of deposit surfaces. The structure is a dense structure of contiguous columns of material. FIG. 4A shows a cross-sectional image of MOSFET device at an intermediate manufacturing process step, including a semiconductor substrate 14, high-k dielectric layer 12 (not yet etched) and a TiN layer 10′, wherein the TiN layer 10′ exhibits a columnar micromorphology, a polysilicon gate electrode 30, and a sidewall spacer 32. The structure of the gate stack has a relatively smooth interface 34 between the TiN layer 10′ and the polysilicon gate electrode 30. Furthermore, TiN layer 10′ exhibits relatively well defined columns 36 (shown in more detail in FIG. 4B). In this regard, columnar grains are noted to be elonged in one direction (for example, in the illustration of FIG. 4B, elongated in a direction perpendicular to the substrate). Such columnar structures are notably more brittle and subject to decohesion when exposed to shock.
The deposition temperature for TiN is, for example, less than 500° C. (which is much lower than the melting point of 2930° C.) in conventional semiconductor processing, and thus it is not possible to achieve an equiaxed grain structure using the conventional processes. The columnar structure of the TiN layer 10′ will accordingly result in undesirable work function variation as shown by FIGS. 3A-3C.
It is further noted that if the deposition of TiN is performed at a high temperature (for example, >300° C.), then there is a risk that the nitrogen added to dielectric gate oxide (for example, made of SiON or high-k materials such as HfSiON or HfON) for the purpose of adjusting the centering of the transistor device will be desorbed. Thus, conventional semiconductor processes used for deposition of the TiN WF metal require an even lower process temperature less than 100° C. (for example, at or about 20° C.) to ensure that the nitrogen is not desorbed.
There is a need in the art for a semiconductor process for the deposition of TiN for the WF metal of a MOSFET conductive gate stack that will produce a micromorphology that is characterized as having equiaxed grains.